A solid-state imaging apparatus (a so-called CCD sensor or CMOS sensor) is widely known as an image sensor used in a digital still camera, a digital video camera, a cell-phone camera, an endoscopic camera and the like. In the solid-state imaging apparatus, photodiode-containing pixels are arranged on a semiconductor substrate such as silicon chip, and signal charges corresponding to photoelectrons generated in the photodiode of each pixel are acquired through a CCD or CMOS reading circuit.
In the solid-state imaging apparatus, not only photodiodes but also signal reading circuits and multilayer interconnections connected thereto are formed in each pixel on a semiconductor substrate. Therefore, the progress of pixel miniaturization is accompanied by a problem of causing a phenomenon that the circuit/interconnection region occupying in one pixel is relatively increased to decrease the light-receiving area of the photodiode, that is, “reduction in the aperture ratio”. The reduction in the aperture ratio leads to a decrease in the light sensitivity during imaging.
To solve such a problem, JP-B-1-34509 (the term “JP-B” as used herein means an “examined published Japanese patent application”) has proposed a so-called stacked solid-state imaging apparatus where a photoelectric conversion layer is stacked above a semiconductor substrate having formed thereon respective circuits and interconnections and the aperture ratio is thereby increased. For example, the imaging apparatus has a configuration such that a large number of photoelectric conversion elements each containing a pixel electrode formed on a semiconductor substrate, a photoelectric conversion layer formed on the pixel electrode and a counter electrode formed on the photoelectric conversion layer are arranged on a plane parallel to the semiconductor substrate. Incidentally, the pixel electrode and the counter electrode are sometimes referred to as a lower electrode and an upper electrode, respectively. In the photoelectric conversion element, an exciton generated in the photoelectric conversion layer upon application of a bias voltage between the pixel electrode and the counter electrode is dissociated into electrons and holes, and signals in proportion to electron or hole charges moved to the pixel electrode according to the bias voltage are acquired through a CCD or CMOS reading circuit provided in the semiconductor substrate.
The photoelectric conversion element is a device where an electric charge is produced in a photoelectric conversion layer according to light incident from the side of a transparent electrode having light transmittance out of a pair of electrodes and the produced electric charge is read as a signal charge from an electrode. As for such a photoelectric conversion element, those described in JP-A-2008-72090 (the term “JP-A” as used herein means an “unexamined published Japanese patent application”) and JP-A-2007-273945 are known.
In JP-A-2008-72090 and JP-A-2007-273945, the photoelectric conversion layer is composed of an organic semiconductor, making it possible to form a thin photoelectric conversion layer while ensuring a large absorption coefficient, whereby less diffusion of an electric charge into the adjacent pixel and reduction in the optical color mixing and electrical color mixing (crosstalk) can be achieved.
JP-A-2008-72090 describes a photoelectric conversion element where a pixel electrode is produced on a transparent substrate such as glass and a transparent electrically conductive oxide (TCO) is used for the material of the pixel electrode.